An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, patterning is used extensively to build various layers of devices which ultimately form the chip or die. For example, the source and drain on an individual IGFET are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. Other devices on other layers are also constructed using patterning formed by placing a photoresist on the structure and then exposing portions of the photoresist to light. A mask is used to mask off parts of the light and to form the necessary patterns on the photoresist. The portion of the photoresist exposed to light may be either removed (positive photomasking) or the unexposed portion may be removed (negative photomasking). The images formed using a mask are very small. For example, some signal carrying lines formed with masks are 0.15 microns or less.
The resolution of small images is affected by several conditions on the wafer surface. Reflections off the surface layers, increasing variation of the topography, and the etching of multilayer stacks all require special process steps.
The high-intensity exposing radiation used to expose the photoresist ideally is directed at a 90.degree. angle to the wafer surface. When this ideal situation exists, exposing waves reflect directly up and down in the resist, leaving a well-defined exposed image. In reality, some of the exposing waves are traveling at angles other than 90.degree. and expose unwanted portions of the resist.
This subsurface reflectivity varies with the surface layer material and the surface smoothness. Metal layers, especially aluminum and aluminum alloys, have higher reflectivity properties. A goal of the deposition processes is a consistent and smooth surface to control this form of reflection.
Reflection problems are intensified on wafers with many steps, also called a varied topography. The sidewalls of the steps reflect radiation at angles into the resist, causing poor image resolution. A particular problem is light interference at the step that causes a "notching" of the pattern as it crosses the step.
Anti-reflective coatings (ARCs) spun onto the wafer surface before the resist can aid the patterning of small images. The ARC layer brings several advantages to the masking process. First is a planarizing of the surface, which makes for a more planarized resist layer. Second, an ARC cuts down on light scattering from the surface into the resist, which helps in the definition of small images. An ARC can also minimize standing wave effects and improve the image contrast. The latter benefit comes from increased exposure latitude with a proper ARC.
An ARC is spun onto the wafer and baked. After the resist is spun on top of the ARC, the wafer is aligned and exposed. The pattern is developed in both the resist and the ARC. During the etch, the ARC acts as an etch barrier. To be effective, an ARC material must transmit light in the same range as the resist. It must also have good adhesion properties with the wafer surface and the resist. Two other requirements are that the ARC must have a refractive index that matches the resist, and that the ARC must develop and be stripped with the same chemicals as the resist.
There are several penalties associated with the use of an ARC. One is an additional layer requiring a separate spin and bake. The resolution gains offered by an ARC can be offset with poor thickness control and/or with an ill-controlled developing step. The time of exposure can increase 30 to 50 percent, increasing the wafer throughput time.
Typically there is a need to connect between layers or form a connection between an exterior surface of a chip or die and a semiconductor within the device. A structure called a via is formed for interconnecting layers or one device or portion internal to the chip and an external surface. A via is a vertical opening filled with conducting material used to connect circuits on various layers of a device to one another and to the semiconducting substrates. Structures formed will typically include one or more vias for interconnecting the various layers of a device. Contacts are vias that form an electrical path to a layer within the device. A layer of devices is typically covered with an etch stop layer of S.sub.i N or S.sub.i ON. A layer of silicon dioxide (SiO.sub.2) or a dielectric layer is then placed over the etch stop layer. A dielectric is a material that conducts no current when it has a voltage placed across it. The dielectric insulates one layer from another layer, or if it is the final layer, the dielectric passivates the top layer of the device formed.
In forming vias for either interconnecting layers within a device or for producing contacts from within the device or chip to an external surface, there are several problems that occur with the current methods for forming a via. After an anti-reflective coating is laid down and baked on, photo resist is placed on the surface of the chip and exposed. Either the unexposed or exposed photoresist is removed (depending upon whether its a positive or negative photoresist) leaving an opening in the photoresist where a via will be formed. Each layer must then be removed through the opening to form a via using a separate etching step. In other words, the ARC must be removed first, then the SiO.sub.2, then the etch stop must then be removed to form a passageway through each of the layers and down to the layer or point to which to connect within the chip. The resist and the ARC, which are the two upper layers or layers most distant from the layer to which to connect, are also removed in separate etching steps. As can be seen, forming a set of vias for a layer requires a number of steps.
In semiconductor fabrication, there is always a need for a process that uses less steps to accomplish the same task. Less steps not only simplifies the process but also provides for less chance for error and therefore improves the reliability of the finished product. In addition, there is a need for a process that lessens the distortion associated with current processing steps. Distortion results in less accurate electrical connection lines formed within a device.